Efficient Hardware Operations for the Residue Number System by Boolean Minimization

DOI10.1007/978-3-030-20323-8_11zbMath1528.68037arXiv1808.03083OpenAlexW2957295841MaRDI QIDQ6181737

Unnamed Author, Tiziano Villa

Publication date: 23 January 2024

Published in: Advanced Boolean Techniques (Search for Journal in Brave)

Full work available at URL: https://arxiv.org/abs/1808.03083

zbMATH Keywords

residue number systemcomputer arithmeticBoolean minimizationmodular multiplicationmodulo function

Mathematics Subject Classification ID

Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.) (68W35) Mathematical problems of computer architecture (68M07)

Cites Work

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• Residue Number Systems
• Modular Multiplication Without Trial Division
• A universal architecture for designing efficient modulo 2/sup n/+1 multipliers
• A New Approach to the Design of Efficient Residue Generators for Arbitrary Moduli
• Cryptographic Hardware and Embedded Systems - CHES 2004

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