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FPGA Implementation of Multi-Layer Machine Learning Equalizer with On-Chip Training - MaRDI portal

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FPGA Implementation of Multi-Layer Machine Learning Equalizer with On-Chip Training

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Publication:6419819

arXiv2212.03515MaRDI QIDQ6419819

Author name not available (Why is that?)

Publication date: 7 December 2022

Abstract: We design and implement an adaptive machine learning equalizer that alternates multiple linear and nonlinear computational layers on an FPGA. On-chip training via gradient backpropagation is shown to allow for real-time adaptation to time-varying channel impairments.












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