Formal verification of speed-dependent asynchronous circuits using symbolic model checking of Branching Time Regular Temporal Logic

DOI10.1007/3-540-55179-4_38MaRDI QIDQ6493558

Kiyoharu Hamaguchi, Shuzo Yajima, Hiromi Hiraishi

Publication date: 29 April 2024

Mathematics Subject Classification ID

Specification and verification (program logics, model checking, etc.) (68Q60)

Cites Work

• Symbolic model checking: \(10^{20}\) states and beyond
• Graph-Based Algorithms for Boolean Function Manipulation
• Automatic Verification of Sequential Circuits Using Temporal Logic
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