Mining of extended signal temporal logic specifications with ParetoLib 2.0
From MaRDI portal
Publication:6564179
DOI10.1007/s10703-024-00453-2MaRDI QIDQ6564179
Thao Dang, Nicolas Basset, José Ignacio Requeno Jarabo, Akshay Mambakam, Alexey Bakhirkin
Publication date: 28 June 2024
Published in: Formal Methods in System Design (Search for Journal in Brave)
Cites Work
- Unnamed Item
- Unnamed Item
- Formal modeling and analysis of timed systems. 18th international conference, FORMATS 2020, Vienna, Austria, September 1--3, 2020. Proceedings
- Logical clustering and learning for time-series data
- STL*: extending signal temporal logic with signal-value freezing operator
- Tools and algorithms for the construction and analysis of systems. 25th international conference, TACAS 2019, held as part of the European joint conferences on theory and practice of software, ETAPS 2019, Prague, Czech Republic, April 6--11, 2019. Proceedings. Part II
- S-TaLiRo: A Tool for Temporal Logic Falsification for Hybrid Systems
- Robust Satisfaction of Temporal Logic over Real-Valued Signals
- Formal Techniques, Modelling and Analysis of Timed and Fault-Tolerant Systems
This page was built for publication: Mining of extended signal temporal logic specifications with ParetoLib 2.0