Glitch and laser fault attacks onto a secure AES implementation on a SRAM-based FPGA

DOI10.1007/s00145-010-9083-9zbMath1239.94040OpenAlexW2079792016MaRDI QIDQ656510

G. Canivet, P. Maistri, J. Clédière, F. Valette, R. Leveugle, Marc Renaudin

Publication date: 18 January 2012

Published in: Journal of Cryptology (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/s00145-010-9083-9

zbMATH Keywords

AESDDRlaser fault injectionspower glitchSRAM-based FPGA

Mathematics Subject Classification ID

Cryptography (94A60) Data encryption (aspects in computer science) (68P25)

Related Items

Learn from your faults: leakage assessment in fault attacks using deep learning

Cites Work

• Unnamed Item
• Unnamed Item
• Unnamed Item
• Unnamed Item
• Double-Data-Rate Computation as a Countermeasure against Fault Analysis
• A Differential Fault Attack Technique against SPN Structures, with Application to the AES and Khazad
• Advanced Encryption Standard – AES
• On the importance of eliminating errors in cryptographic computations