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Graph methods for recognition of CMOS gates in transistor-level circuits - MaRDI portal

Graph methods for recognition of CMOS gates in transistor-level circuits

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Publication:6573399

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DOI10.17223/20710410/64/4MaRDI QIDQ6573399

L. D. Cheremisinova, Dmitrij I. Cheremisinov

Publication date: 16 July 2024

Published in: Prikladnaya Diskretnaya Matematika (Search for Journal in Brave)

zbMATH Keywords

graph isomorphism CMOS transistor circuit logic gate recognition SPICE format subcircuit extraction

Mathematics Subject Classification ID

Computer science (68-XX) Information and communication theory, circuits (94-XX)

Cites Work

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