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Efficient arithmetic in garbled circuits

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Publication:6637536
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DOI10.1007/978-3-031-58740-5_1MaRDI QIDQ6637536

David G. Heath

Publication date: 13 November 2024





zbMATH Keywords

arithmetic circuitsgarbled circuits


Mathematics Subject Classification ID

Computer science (68-XX)


Cites Work

  • Title not available (Why is that?)
  • Three halves make a whole? Beating the half-gates lower bound for garbled circuits
  • Arithmetic garbling from bilinear maps
  • Fast garbling of circuits under standard assumptions
  • Integer multiplication in time \(O(n\log n)\)
  • FleXOR: Flexible Garbling for XOR Gates That Beats Free-XOR
  • On the Security of the “Free-XOR” Technique
  • Two Halves Make a Whole
  • Improved Garbled Circuit: Free XOR Gates and Applications
  • Secure Two-Party Computation Is Practical
  • How to Garble RAM Programs?
  • How to Garble Arithmetic Circuits
  • New ways to garble arithmetic circuits
  • Half-tree: halving the cost of tree expansion in COT and DPF
  • Tri-state circuits. A circuit model that captures RAM


Related Items (2)

Garbled circuit lookup tables with logarithmic number of ciphertexts ⋮ Scalable multiparty computation from non-linear secret sharing






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