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A neural network accelerated optimization method for FPGA - MaRDI portal

A neural network accelerated optimization method for FPGA

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Publication:6645179

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DOI10.1007/s10878-024-01117-xMaRDI QIDQ6645179

Leilei Wang, Zhiyuan Xie, Wangbin Cao, Sijie Zhu, Zhengwei Hu

Publication date: 28 November 2024

Published in: Journal of Combinatorial Optimization (Search for Journal in Brave)

zbMATH Keywords

neural network high-level synthesis field programmable gate array hardware acceleration Mitchell algorithm

Mathematics Subject Classification ID

Mathematical programming (90Cxx)

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