A note on digital filter implementation using hybrid RNS-binary arithmetic

DOI10.1016/0165-1684(96)00031-XzbMATH Open0925.94033MaRDI QIDQ671282

Behrooz Parhami

Publication date: 27 February 1997

Published in: Signal Processing (Search for Journal in Brave)

zbMATH Keywords

VLSI architecturesDigital filtersInner productRNS arithmetic

Mathematics Subject Classification ID

Signal theory (characterization, reconstruction, filtering, etc.) (94A12) Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.) (68W35)

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