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Reduced interprocessor-communication architecture and its implementation on EM-4 - MaRDI portal

Reduced interprocessor-communication architecture and its implementation on EM-4

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Publication:673526

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DOI10.1016/0167-8191(94)00109-NzbMath0875.68171MaRDI QIDQ673526

Hiroshi Matsuoka, Shuichi Sakai, Yuetsu Kodama, Mitsuhisa Sato, Andrew P. Shaw

Publication date: 28 February 1997

Published in: Parallel Computing (Search for Journal in Brave)

zbMATH Keywords

Interprocessor communication EM-4 prototype Massively parallel computers Programming models RICA (reduced interprocessor-communication architecture)

Mathematics Subject Classification ID

Computer system organization (68M99) Theory of software (68N99)

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