Gate-delay-fault testability properties of multiplexor-based networks

DOI10.1007/BF01383945zbMath0777.94027MaRDI QIDQ685105

Kurt Keutzer, Srinivas Devadas, Pranav Ashar

Publication date: 30 September 1993

Published in: Formal Methods in System Design (Search for Journal in Brave)

zbMATH Keywords

logic circuitsBinary Decision Diagramgate-delay faultsstuck-at faultssynthesis for test

Mathematics Subject Classification ID

Fault detection; testing in circuits and networks (94C12)

Cites Work

• Graph-Based Algorithms for Boolean Function Manipulation
• Binary Decision Diagrams
• Unnamed Item