Asynchronous datapaths and the design of an asynchronous adder

DOI10.1007/BF00464358zbMath0777.94023OpenAlexW2021330840MaRDI QIDQ685122

Alain J. Martin

Publication date: 30 September 1993

Published in: Formal Methods in System Design (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/bf00464358

zbMATH Keywords

asynchronous addersdelay-insensitive datapath circuitsripple-carry adder

Mathematics Subject Classification ID

Cites Work

• Compiling communicating processes into delay-insensitive VLSI circuits
• Unnamed Item

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