Design of a pipelined radix 4 CORDIC processor

DOI10.1016/0167-8191(93)90061-OzbMath0774.68019OpenAlexW2048482282MaRDI QIDQ686627

Emilio L. Zapata, Javier D. Bruguera, Elisardo Antelo

Publication date: 10 October 1993

Published in: Parallel Computing (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1016/0167-8191(93)90061-o

zbMATH Keywords

CORDIC algorithmdigital signal processingpipeliningredundant arithmeticsigned-digit adders

Mathematics Subject Classification ID

Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.) (68W35) Computer system organization (68M99)

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