Using bus linearization to scale the reconfigurable mesh
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Publication:697001
DOI10.1006/jpdc.2001.1810zbMath1015.68017OpenAlexW2046931864MaRDI QIDQ697001
José Alberto Fernández-Zepeda, Ramachandran Vaidyanathan, Jerry L. Trahan
Publication date: 12 September 2002
Published in: Journal of Parallel and Distributed Computing (Search for Journal in Brave)
Full work available at URL: https://doi.org/10.1006/jpdc.2001.1810
reconfigurable meshalgorithm scalabilitybusbus linearizationconcurrent write rulespipelined opticalreconfigurable architectures and algorithms
Related Items (4)
SIMULATION OF MESHES WITH SEPARABLE BUSES BY MESHES WITH MULTIPLE PARTITIONED BUSES ⋮ EFFICIENT SIMULATION OF AN ACYCLIC DIRECTED RECONFIGURABLE MODEL ON AN UNDIRECTED RECONFIGURABLE MODEL ⋮ DESIGNING FAULT TOLERANT ALGORITHMS FOR RECONFIGURABLE MESHES ⋮ SIMULATING AN R-MESH ON AN LR-MESH IN CONSTANT TIME
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