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Multiple addition and prefix sum on a linear array with a reconfigurable pipelined bus system

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Publication:704695
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DOI10.1023/B:SUPE.0000032783.66123.63zbMath1084.68009MaRDI QIDQ704695

Amitava Datta

Publication date: 19 January 2005

Published in: The Journal of Supercomputing (Search for Journal in Brave)


zbMATH Keywords

additionmatrix multiplicationOptical computingpipelined busprefix sumreconfigurable bus


Mathematics Subject Classification ID

Analysis of algorithms (68W40) Mathematical problems of computer architecture (68M07) Distributed algorithms (68W15)


Related Items (1)

A class of almost-optimal size-independent parallel prefix circuits







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