A practical bytecode interpreter for programmable routers on IXP network processors

DOI10.1016/J.COMNET.2009.06.007zbMath1187.68096OpenAlexW2152590153MaRDI QIDQ733244

S. Martin, Guy Leduc

Publication date: 15 October 2009

Published in: Computer Networks (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1016/j.comnet.2009.06.007

zbMATH Keywords

performance analysisbytecodenetwork processorprogrammable router

Mathematics Subject Classification ID

Performance evaluation, queueing, and scheduling in the context of computer systems (68M20) Internet topics (68M11)

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