Testable design of AND-EXOR logic networks with universal test sets

DOI10.1016/j.compeleceng.2009.01.006zbMath1187.68048OpenAlexW1971693568MaRDI QIDQ733292

Debesh K. Das, Hafizur Rahaman, Bhargab Bikram Bhattacharya

Publication date: 15 October 2009

Published in: Computers and Electrical Engineering (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1016/j.compeleceng.2009.01.006

zbMATH Keywords

BISTdesign-for-testabilityGRM/ESOP networkstuck-at and bridging faultsuniversal test set

Mathematics Subject Classification ID

Network design and communication in computer systems (68M10)

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