Efficient realization of large size two's complement multipliers using embedded blocks in FPGAs

DOI10.1007/S00034-008-9051-XzbMath1173.93339OpenAlexW2088602259MaRDI QIDQ733691

Noureddine Chabini, Dhamin Al-Khalili, Shuli Gao

Publication date: 19 October 2009

Published in: Circuits, Systems, and Signal Processing (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/s00034-008-9051-x

zbMATH Keywords

Baugh-Wooley algorithmembedded blocks in FPGAslarge size multipliertwo's complement number

Mathematics Subject Classification ID

Design techniques (robust design, computer-aided design, etc.) (93B51)

Uses Software

• Xilinx

Cites Work

• A Two's Complement Parallel Array Multiplication Algorithm
• Unnamed Item

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