A low-memory-access length-adaptive architecture for \(2^n\)-point FFT

DOI10.1007/S00034-014-9862-XzbMath1401.94028OpenAlexW2012256636MaRDI QIDQ736386

Kuan-Hung Chen

Publication date: 4 August 2016

Published in: Circuits, Systems, and Signal Processing (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/s00034-014-9862-x

zbMATH Keywords

FFTVLSI architectureenergy-efficientlength-adaptivelong-length

Mathematics Subject Classification ID

Signal theory (characterization, reconstruction, filtering, etc.) (94A12) Numerical methods for discrete and fast Fourier transforms (65T50)

Cites Work

• The efficient memory-based VLSI array designs for DFT and DCT
• A High-Throughput Radix-16 FFT Processor With Parallel and Normal Input/Output Ordering for IEEE 802.15.3c Systems
• High-speed and low-power split-radix FFT

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