High-throughput architectures for circular block-type low-density parity-check codes

DOI10.1007/s00034-015-9993-8zbMath1358.94090OpenAlexW1978689362MaRDI QIDQ736977

Meng-Yi Lin, Kuang-Hao Lin

Publication date: 5 August 2016

Published in: Circuits, Systems, and Signal Processing (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/s00034-015-9993-8

zbMATH Keywords

VLSIerror correction codeschannel codinglow-density parity-check (LDPC)quasicyclic

Mathematics Subject Classification ID

Linear codes (general theory) (94B05)

Uses Software

• LDPC

Cites Work

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• Memory System Optimization for FPGA-Based Implementation of Quasi-Cyclic LDPC Codes Decoders
• A High-Throughput LDPC Decoder Architecture With Rate Compatibility