Triple-matrix product-based 2D systolic implementation of discrete Fourier transform

DOI10.1007/S00034-015-9990-YzbMath1367.68014OpenAlexW2074146639MaRDI QIDQ737012

T. S. B. Sudarshan, I. Mamatha, Nikhil Bhattar, Shikha Tripathi

Publication date: 5 August 2016

Published in: Circuits, Systems, and Signal Processing (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/s00034-015-9990-y

zbMATH Keywords

fast Fourier transformdiscrete Fourier transformVLSIFPGAsystolic array architecture

Mathematics Subject Classification ID

Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.) (68W35) Numerical methods for discrete and fast Fourier transforms (65T50) Mathematical problems of computer architecture (68M07)

Cites Work

• Efficient VLSI architectures for fast computation of the discrete Fourier transform and its inverse
• A new systolic array for discrete Fourier transform
• A new linear systolic array for FFT computation
• An Algorithm for the Machine Calculation of Complex Fourier Series
• High-speed and low-power split-radix FFT
• Computationally efficient systolic architecture for computing the discrete Fourier transform

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