Complexities of layouts in three-dimensional VLSI circuits

DOI10.1016/0020-0255(91)90012-JzbMath0716.94019OpenAlexW2041062241MaRDI QIDQ753802

Mokhtar A. Aboelaze, Benjamin W.-S. Wah

Publication date: 1991

Published in: Information Sciences (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1016/0020-0255(91)90012-j

Mathematics Subject Classification ID

Related Items (1)

Geometric thickness in a grid

Cites Work

• Unnamed Item
• A framework for solving VLSI graph layout problems
• Three-Dimensional VLSI
• Three-Dimensional Circuit Layouts
• New lower bound techniques for VLSI
• Optimal three-dimensional VLSI layouts

This page was built for publication: Complexities of layouts in three-dimensional VLSI circuits