A systolic array with applications to image processing and wire-routing in VLSI circuits

DOI10.1016/S0167-8191(05)80020-1zbMath0723.68009OpenAlexW1971505705MaRDI QIDQ757007

D. Kharzeev

Publication date: 1991

Published in: Parallel Computing (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1016/s0167-8191(05)80020-1

zbMATH Keywords

image processingmorphologycircuit layout

Mathematics Subject Classification ID

Computing methodologies for image processing (68U10) Circuits, networks (94C99) General theory of computer systems (68M01)

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