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The design and time analysis of a systolic array with asynchronous protocols for matrix multiplication - MaRDI portal

The design and time analysis of a systolic array with asynchronous protocols for matrix multiplication

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Publication:805231

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DOI10.1016/0045-7906(89)90018-9zbMath0728.68060OpenAlexW2093515745MaRDI QIDQ805231

Shietung Peng, Moon S. Jun

Publication date: 1989

Published in: Computers and Electrical Engineering (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1016/0045-7906(89)90018-9

zbMATH Keywords

systolic arrays recursive algorithms matrix multiplication Transputer asynchronous arrays

Mathematics Subject Classification ID

Computational methods for sparse matrices (65F50) Parallel algorithms in computer science (68W10) Numerical linear algebra (65F99)

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