A formal approach to designing delay-insensitive circuits

DOI10.1007/BF02252954zbMath0731.68081MaRDI QIDQ808286

Jo C. Ebergen

Publication date: 1991

Published in: Distributed Computing (Search for Journal in Brave)

zbMATH Keywords

regular expressionsasynchronous circuittrace semanticscommunication behaviordelay- insensitive circuits

Mathematics Subject Classification ID

Circuits, networks (94C99) Models and methods for concurrent and distributed computing (process algebras, bisimulation, transition nets, etc.) (68Q85)

Related Items (5)

The Theta-Model: achieving synchrony without clocks ⋮ Reconciling fault-tolerant distributed computing and systems-on-chip ⋮ Diagrammatic Reasoning for Delay-Insensitive Asynchronous Circuits ⋮ The asynchronous bounded-cycle model ⋮ Delay-insensitivity and ternary simulation

Cites Work

• Compiling communicating processes into delay-insensitive VLSI circuits
• Trace theory and VLSI design
• Communicating sequential processes
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