Register saturation in instruction level parallelism

DOI10.1007/S10766-005-6466-XzbMath1086.68519OpenAlexW2058372704MaRDI QIDQ816220

Sid-Ahmed-Ali Touati

Publication date: 20 February 2006

Published in: International Journal of Parallel Programming (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/s10766-005-6466-x

zbMATH Keywords

integer linear programminginstruction level parallelismoptimizing compilationregister pressureRegister requirement

Mathematics Subject Classification ID

Performance evaluation, queueing, and scheduling in the context of computer systems (68M20) Computer system organization (68M99)

Cites Work

• On a graph-theoretical model for cyclic register allocation
• Dual-Issue Scheduling for Binary Trees with Spills and Pipelined Loads
• Scheduling Arithmetic and Load Operations in Parallel with No Spilling
• Unnamed Item
• Unnamed Item

This page was built for publication: Register saturation in instruction level parallelism