High speed and computationally efficient architecture for recursive interpolation filters

DOI10.1016/J.SIGPRO.2009.04.037zbMath1169.94311OpenAlexW2024765123MaRDI QIDQ839078

Habibullah Jamal, Shoab Ahmed Khan, Umar Farooq

Publication date: 1 September 2009

Published in: Signal Processing (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1016/j.sigpro.2009.04.037

zbMATH Keywords

computational efficiencyFPGAinterpolation filtersmerged delay transformation

Mathematics Subject Classification ID

Filtering in stochastic control theory (93E11) Signal theory (characterization, reconstruction, filtering, etc.) (94A12)

Uses Software

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Cites Work

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• Low-power decimator design using approximated linear-phase N-band IIR filter
• On the synthesis of very sharp decimators and interpolators using the frequency-response masking technique

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