Verification of FPGA layout generators in higher-order logic

DOI10.1007/S10817-006-9039-9zbMath1113.68092OpenAlexW2013832163MaRDI QIDQ877830

Oliver Pell

Publication date: 3 May 2007

Published in: Journal of Automated Reasoning (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/s10817-006-9039-9

zbMATH Keywords

layout descriptionsroute algorithms

Mathematics Subject Classification ID

Specification and verification (program logics, model checking, etc.) (68Q60)

Uses Software

• Isabelle
• ML
• Isabelle/HOL
• CHIP
• Haskell
• Xilinx
• Lava

Cites Work

• A theory of type polymorphism in programming
• Isabelle/HOL. A proof assistant for higher-order logic
• Correct Hardware Design and Verification Methods
• The Principal Type-Scheme of an Object in Combinatory Logic
• Higher Order Logic and Hardware Verification
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