The method of parallel-sequential built-in self-testing in integrated circuits of the type sFPGAs

DOI10.1134/S0005117907010146zbMath1195.94098MaRDI QIDQ885846

V. F. Khalchev, G. P. Aksenova

Publication date: 14 June 2007

Published in: Automation and Remote Control (Search for Journal in Brave)

Mathematics Subject Classification ID

Analytic circuit theory (94C05)

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Compaction of test response at self-testing in the programmable logic matrices ⋮ Design of the EPLD-based reconfigurable fault-tolerant systems with cell-level redundancy

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