Optimal tradeoffs for addition on systolic arrays

DOI10.1007/BF01759034zbMath0703.68058MaRDI QIDQ916387

Alok Aggarwal, J. Lawrence Carter, S. Rao Kosaraju

Publication date: 1991

Published in: Algorithmica (Search for Journal in Brave)

zbMATH Keywords

areaadditionVLSI circuitsboundary layoutsinput/output portsworst-case time

Mathematics Subject Classification ID

Cites Work

• Unnamed Item
• Area-time lower-bound techniques with applications to sorting
• The complexity of a VLSI adder
• A model of computation for VLSI with related complexity results
• Speed of Recognition of Context-Free Languages by Array Automata

This page was built for publication: Optimal tradeoffs for addition on systolic arrays