Efficient address generation in a parallel processor

DOI10.1016/0020-0190(90)90078-CzbMath0704.68009OpenAlexW2090048923MaRDI QIDQ917271

De-Lei Lee

Publication date: 1990

Published in: Information Processing Letters (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1016/0020-0190(90)90078-c

zbMATH Keywords

parallel processormemory address generationparallel memory system

Mathematics Subject Classification ID

Analysis of algorithms and problem complexity (68Q25) Computer system organization (68M99)

Cites Work

• Access and Alignment of Data in an Array Processor
• Theoretical Limitations on the Efficient Use of Parallel Memories
• The Organization and Use of Parallel Memories

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