Performance analysis of greedy heuristic to find a minimum total-jogs layout for river routing

DOI10.1016/0020-0190(90)90067-8zbMath0704.68060OpenAlexW2005736921MaRDI QIDQ917314

Tai-Ching Tuan, Kim-Heng Teo

Publication date: 1990

Published in: Information Processing Letters (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1016/0020-0190(90)90067-8

zbMATH Keywords

VLSI layoutapproximation boundriver routinggreedy approachtotal jogs minimization

Mathematics Subject Classification ID

Analysis of algorithms and problem complexity (68Q25) Parallel algorithms in computer science (68W10) Circuits, networks (94C99)

Related Items (1)

Performance analysis of greedy heuristic to find a minimum total-jogs layout for river routing

Cites Work

• Unnamed Item
• Performance analysis of greedy heuristic to find a minimum total-jogs layout for river routing
• River routing in VLSI
• An optimal solution to a wire-routing problem
• River Routing with a Small Number of Jogs
• Optimal Placement for River Routing

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