Retiming synchronous circuitry
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Publication:920937
DOI10.1007/BF01759032zbMath0708.94025MaRDI QIDQ920937
Charles E. Leiserson, James B. Saxe
Publication date: 1991
Published in: Algorithmica (Search for Journal in Brave)
network floworganizationretimingcircuit transformationcombinational logic elementsmixed-integer linear- programmingpipelining combinational circuitrysynchronous circuitsystolic circuitsVLSI design automation
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- Efficient Algorithms for Shortest Paths in Sparse Networks
- Fibonacci heaps and their uses in improved network optimization algorithms
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