Partitioning circuits for improved testability

DOI10.1007/BF01759033zbMath0708.94026OpenAlexW1966833457MaRDI QIDQ920939

Sandeep N. Bhatt, Fan R. K. Chung, Arnold L. Rosenberg

Publication date: 1991

Published in: Algorithmica (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/bf01759033

zbMATH Keywords

dynamic programmingNP-completenessVLSI circuitscombinational logiclevel-sensitive scan designself-testing of combinational circuitryunconstrained partitioning problem

Mathematics Subject Classification ID

Analysis of algorithms and problem complexity (68Q25) Dynamic programming (90C39) Fault detection; testing in circuits and networks (94C12)

Related Items (2)

A graph partitioning heuristic for the parallel pseudo-exhaustive logical test of VLSI combinational circuits ⋮ Minimal length test vectors for multiple-fault detection

Cites Work

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• Exhaustive Test Pattern Generation with Constant Weight Vectors
• Exhaustive Generation of Bit Patterns with Applications to VLSI Self-Testing
• Testing by Feedback Shift Register

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