Design of the EPLD-based reconfigurable fault-tolerant systems with cell-level redundancy

DOI10.1134/S0005117907090172zbMath1147.93338MaRDI QIDQ927556

S. S. Uvarov

Publication date: 9 June 2008

Published in: Automation and Remote Control (Search for Journal in Brave)

Mathematics Subject Classification ID

Reliability, availability, maintenance, inspection in operations research (90B25) Control/observation systems involving computers (process control, etc.) (93C83) Design techniques (robust design, computer-aided design, etc.) (93B51)

Related Items (1)

Localization of faulty multi-output unit in discrete device

Cites Work

• The method of parallel-sequential built-in self-testing in integrated circuits of the type sFPGAs
• Minimized embedding of arbitrary Hamiltonian graphs in fault-tolerant graph and reconfiguration at faults. II: Grids and \(k\)-fault-tolerance
• Minimized embedding of arbitrary Hamiltonian graphs in fault-tolerant graph and reconfiguration at faults. I: One-fault-tolerant structures

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