Dynamic instruction scheduling in a trace-based multi-threaded architecture

DOI10.1007/S10766-007-0062-1zbMath1147.68414OpenAlexW2021739830MaRDI QIDQ934716

Alberto F. De Souza, Peter A. Rounce

Publication date: 30 July 2008

Published in: International Journal of Parallel Programming (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/s10766-007-0062-1

zbMATH Keywords

VLIWDynamic instruction schedulingSimultaneous multi-threadingWide issue architectures

Mathematics Subject Classification ID

Performance evaluation, queueing, and scheduling in the context of computer systems (68M20) Computer system organization (68M99)

Cites Work

• Unnamed Item
• Multithreaded Processors
• Dynamically scheduling VLIW instructions

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