Performance advantage of reconfigurable cache design on multicore processor systems

DOI10.1007/s10766-008-0075-4zbMath1147.68419OpenAlexW2164157607MaRDI QIDQ934956

Marcel Kunze, Rainer Buchty, Fabian Nowak, Jie Tao, Wolfgang Karl

Publication date: 31 July 2008

Published in: International Journal of Parallel Programming (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/s10766-008-0075-4

zbMATH Keywords

simulationreconfigurable architecturecache performancemulticore processor

Mathematics Subject Classification ID

Performance evaluation, queueing, and scheduling in the context of computer systems (68M20) Computer system organization (68M99)

Uses Software

• Valgrind
• NAS Parallel Benchmarks

Cites Work

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