Reconfigurable multiplier blocks: Structures, algorithm and applications

DOI10.1007/S00034-007-9005-8zbMath1151.68313OpenAlexW2022312970MaRDI QIDQ941162

Izzet Kale, Süleyman Sırrı Demirsoy, Andrew G. Dempster

Publication date: 4 September 2008

Published in: Circuits, Systems, and Signal Processing (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/s00034-007-9005-8

zbMATH Keywords

reduced complexity fixed multiplierstime-multiplexed multiple constant multiplications

Mathematics Subject Classification ID

Mathematical problems of computer architecture (68M07)

Cites Work

• Constant integer multiplication using minimum adders
• Use of minimum-adder multiplier blocks in FIR digital filters
• Minimum number of adders for implementing a multiplier and its application to the design of multiplierless digital filters

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