Semi-formal verification of the steady state behavior of mixed-signal circuits by SAT-based property checking

DOI10.1016/j.tcs.2008.03.032zbMath1293.68193OpenAlexW2021724238MaRDI QIDQ947801

Jörg Bormann, Jens Schönherr, Bernd Straube, Martin Freibothe

Publication date: 7 October 2008

Published in: Theoretical Computer Science (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1016/j.tcs.2008.03.032

zbMATH Keywords

formal verificationmixed-signalproperty checkingVHDL behavioral description

Mathematics Subject Classification ID

Specification and verification (program logics, model checking, etc.) (68Q60) Analytic circuit theory (94C05) Mathematical aspects of software engineering (specification, verification, metrics, requirements, etc.) (68N30)

Uses Software

• PHAVer
• HyTech
• Chaff

Cites Work

• Observability and controllability of piecewise affine and hybrid systems
• Hybrid Systems: Computation and Control
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