Models and formal verification of multiprocessor system-on-chips

DOI10.1016/j.jlap.2008.05.002zbMath1151.68339OpenAlexW2047516333WikidataQ54483958 ScholiaQ54483958MaRDI QIDQ953526

Jan Madsen, Michael R. Hansen, Aske W. Brekling

Publication date: 6 November 2008

Published in: The Journal of Logic and Algebraic Programming (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1016/j.jlap.2008.05.002

zbMATH Keywords

verificationtimed automataschedulabilitymultiprocessor system-on-chipsuppaal

Mathematics Subject Classification ID

Performance evaluation, queueing, and scheduling in the context of computer systems (68M20) Specification and verification (program logics, model checking, etc.) (68Q60)

Related Items (4)

A hybrid performance analysis technique for distributed real-time embedded systems ⋮ Model Checking Real-Time Systems ⋮ Research and Development of an Algorithm for the Response Time Estimation in Multiprocessor Systems Under the Interval Uncertainty of the Tasks Execution Times ⋮ Formal verification and quantitative metrics of MPSoC data dynamics

Uses Software

• TIMES
• SPIN
• Uppaal
• legOS

Cites Work

• A theory of timed automata
• Uppaal in a nutshell
• Scheduling with timed automata
• Formal Methods for the Design of Real-Time Systems
• Bounds on Multiprocessing Timing Anomalies
• Formal Modeling and Analysis of Timed Systems
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