Area-time tradeoffs for universal VLSI circuits

DOI10.1016/j.tcs.2008.08.005zbMath1157.68020OpenAlexW2017830172MaRDI QIDQ959803

Sandeep N. Bhatt, Gianfranco Bilardi, Geppino Pucci

Publication date: 12 December 2008

Published in: Theoretical Computer Science (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1016/j.tcs.2008.08.005

zbMATH Keywords

interconnection networksarea-universal networksVLSI theory

Mathematics Subject Classification ID

Computer system organization (68M99)

Cites Work

• Unnamed Item
• A framework for solving VLSI graph layout problems
• A lower bound for area-universal graphs
• Efficient Simulations among Several Models of Parallel Computers
• Randomized Routing and Sorting on Fixed-Connection Networks
• Deterministic on-line routing on area-universal networks
• Optimal Rearrangeable Multistage Connecting Networks

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