Yield analysis of partial defect tolerant bit-plane array

DOI10.1016/j.camwa.2009.08.068zbMath1189.90046OpenAlexW2040863065MaRDI QIDQ980319

I. Z. Milentijević, Vladimir Ciric, Aleksandar S. Cvetković

Publication date: 28 June 2010

Published in: Computers \& Mathematics with Applications (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1016/j.camwa.2009.08.068

zbMATH Keywords

systolic arrayserror toleranceeffective yieldpartial defect tolerance

Mathematics Subject Classification ID

Related Items (1)

Tropical algebra based framework for error propagation analysis in systolic arrays

Cites Work

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