Thread-parallel integrated test pattern generator utilizing satisfiability analysis

DOI10.1007/s10766-009-0124-7zbMath1197.68026OpenAlexW2156640787MaRDI QIDQ987743

Matthew Lewis, Ilia Polian, Bernd Becker, Alexander Czutro, Sudhakar M. Reddy, Piet Engelke

Publication date: 13 August 2010

Published in: International Journal of Parallel Programming (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/s10766-009-0124-7

zbMATH Keywords

SAT-based automatic test pattern generationthread-parallel SAT

Mathematics Subject Classification ID

Reliability, testing and fault tolerance of networks and computer systems (68M15)

Related Items

Preprocessing for DQBF ⋮ Solving dependency quantified Boolean formulas using quantifier localization ⋮ Dependency Schemes for DQBF ⋮ The (D)QBF Preprocessor HQSpre – Underlying Theory and Its Implementation1

Uses Software

• MPI
• PaMiraXT

Cites Work

• An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits
• Diagnosis of Automata Failures: A Calculus and a Method
• A Computing Procedure for Quantification Theory
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