FPGA based high performance double-precision matrix multiplication

DOI10.1007/s10766-010-0131-8zbMath1206.68069OpenAlexW4249774071MaRDI QIDQ987759

Siddharth Joshi, Vinay B. Y. Kumar, Sachin B. Patkar, H. Narayanan

Publication date: 13 August 2010

Published in: International Journal of Parallel Programming (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/s10766-010-0131-8

zbMATH Keywords

scalabilityhigh performance computingmatrix multiplicationFPGA implementationmemory-bandwidth trade-offrank-1 scheme

Mathematics Subject Classification ID

Performance evaluation, queueing, and scheduling in the context of computer systems (68M20) Mathematical problems of computer architecture (68M07) Computer system organization (68M99)

Related Items (1)

FPGA based high performance double-precision matrix multiplication

Uses Software

• BLAS

Cites Work

• FPGA based high performance double-precision matrix multiplication

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