SEC-DED

swMATH3207MaRDI QIDQ15740

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Described by source

• Construction techniques for systematic SEC-DED codes with single byte error detection and partial correction capability for computer memory systems

Related Items (16)

Unnamed Item ⋮ A Self-Checking Generalized Prediction Checker and Its Use for Built-In Testing ⋮ A class of error-locating codes for byte-organized memory systems ⋮ A Construction Method of High-Speed Decoders Using ROM's for Bose–Chaudhuri–Hocquenghem and Reed–Solomon Codes ⋮ Binary set functions and parity check matrices ⋮ Linear sum codes for random access memories ⋮ Implementation of an Experimental Fault-Tolerant Memory System ⋮ On Generating the N-ary Reflected Gray Codes ⋮ A Class of Odd-Weight-Column SEC-DED-SbED Codes for Memory System Applications ⋮ Measurement and Generation of Error Correcting Codes for Package Failures ⋮ A Class of Linear Codes for Error Control in Byte-per-Card Organized Digital Systems ⋮ Erasure and Error Decoding for Semiconductor Memories ⋮ SEC-DED Nonbinary Code for Fault-Tolerant Byte-Organized Memory Implemented with Quaternary Logic ⋮ On-line testing for VLSI: state of the art and trends ⋮ Single Byte Error Correcting—Double Byte Error Detecting Codes for Memory Systems ⋮ SEC-BED-DED Codes for Error Control in Byte-Organized Memory Systems

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