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Related Items (28)

Automatic design of application specific instruction set extensions through dataflow graph explorationEvaluation and choice of various branch predictors for low-power embedded processorAUSPICE-R: Automatic Safety-Property Proofs for Realistic Features in Machine CodeEvaluating the Kernighan-Lin Heuristic for Hardware/Software PartitioningUnnamed ItemThe QC-2 parallel queue processor architectureAn algorithm for finding input-output constrained convex sets in an acyclic digraphModulo path history for the reduction of pipeline overheads in path-based neural branch predictorsEmbedded-TM: energy and complexity-effective hardware transactional memory for embedded multicore systemsUsing on-chip networks to implement polymorphism in the co-design of object-oriented embedded systemsFinding optimal hardware/software partitionsA novel instruction stream buffer for VLIW architecturesUsing FORAY models to enable MPSoC memory optimizationsUnnamed ItemNon-blocking Patricia tries with replace operationsHybrid Heuristics for Optimizing Energy Consumption in Embedded SystemsCode transformations for TLB power reductionImproving adaptability and per-core performance of many-core processors through reconfigurationA profile-based tool for finding pipeline parallelism in sequential programsThe ArchC architecture description language and toolsHardware/software optimization for array {\&} pointer boundary checking against buffer overflow attacksProbabilistic analysis of steady-state temperature and maximum frequency of multicore processors considering workload variationSpeculative parallelization of sequential loops on multicoresA compiler-hardware approach to software protection for embedded systemsAlgorithms for generating convex sets in acyclic digraphsSigma*An exact algorithm for the sequential ordering problem and its application to switching energy minimization in compilersEnergy-aware assignment and scheduling for hybrid main memory in embedded systems


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