Modelling and verification of delay-insensitive circuits using CCS and the concurrency workbench
type: Item
instance of: scholarly article
title: Modelling and verification of delay-insensitive circuits using CCS and the concurrency workbench
zbMATH Open document ID: 1183.68387
author: Hemangee K. Kapoor
author: Mark B. Josephs
published in: Information Processing Letters
publication date: 2009-07-09T00:00:00Z
Mathematics Subject Classification ID: 68Q65
zbMATH DE Number: 5576956
zbMATH Keywords: formal methods
zbMATH Keywords: specification languages
zbMATH Keywords: formal verification
zbMATH Keywords: asynchronous logic
describes a project that uses: Concurrency Workbench
MaRDI profile type: Publication
full work available at URL: j.ipl.2003.12.007
OpenAlex ID: W2093834030
cites work: Handshake Circuits
cites work: Q3997501
cites work: Q3777424
cites work: Receptive process theory
cites work: Q4951152
cites work: Q3992568
cites work: Trace theory and VLSI design
cites work: Q4289325
DOI: 10.1016/J.IPL.2003.12.007
description: scientific article; zbMATH DE number 5576956