Floorplan design of VLSI circuits
type: Item
instance of: scholarly article
title: Floorplan design of VLSI circuits
zbMATH Open document ID: 0661.94025
DOI: 10.1007/BF01553890
author: S. H. Smith
published in: Algorithmica
publication date: 1989-01-01T00:00:00Z
review text: In this paper we present two algorithms for the floorplan design problem. The algorithms are quite similar in spirit. They both use Polish expressions to represent floorplans and employ the search method of simulated annealing. The first algorithm is for the case where all modules are rectangular, and the second one is for the case where the modules are either rectangular or L-shaped. Our algorithms consider simultaneously the interconnection information as well as the area and shape information for the modules. Experimental results indicate that our algorithms perform well for many test problems.
Mathematics Subject Classification ID: 94C10
zbMATH DE Number: 4081473
zbMATH Keywords: VLSI circuit layout
zbMATH Keywords: floorplan design
zbMATH Keywords: simulated annealing
describes a project that uses: TimberWolf
MaRDI profile type: Publication
cites work: Q4091421
cites work: Optimization by Simulated Annealing
cites work: Optimal orientations of cells in slicing floorplan designs
description: scientific article; zbMATH DE number 4081473