Counting the number of fault patterns in redundant VLSI arrays
type: Item
instance of: scholarly article
title: Counting the number of fault patterns in redundant VLSI arrays
zbMATH Open document ID: 0796.94022
DOI: 10.1016/0020-0190(94)00047-6
author: L. Pagli
author: Geppino Pucci
published in: Information Processing Letters
publication date: 1994-07-21T00:00:00Z
Mathematics Subject Classification ID: 94C12
Mathematics Subject Classification ID: 68M20
zbMATH DE Number: 609774
zbMATH Keywords: distributed systems
zbMATH Keywords: fault tolerance
zbMATH Keywords: parallel processing
zbMATH Keywords: performance evaluation
zbMATH Keywords: VLSI circuits
zbMATH Keywords: upper and lower bounds
zbMATH Keywords: number of minimal fault patterns
MaRDI profile type: Publication
full work available at URL: 0020-0190(94)00047-6
OpenAlex ID: W2089845810
cites work: Q4040797
cites work: Configuration of VLSI Arrays in the Presence of Defects
cites work: On testing for catastrophic faults in reconfigurable arrays with arbitrary link redundancy
description: scientific article; zbMATH DE number 609774