CMOS realization of all-positive pinched hysteresis loops
type: Item
instance of: scholarly article
title: CMOS realization of all-positive pinched hysteresis loops
zbMATH Open document ID: 1373.94954
DOI: 10.1155/2017/7863095
author: B. J. Maundy
author: A. S. Elwakil
author: Costas Psychalinos
published in: Complexity
publication date: 2017-10-26T00:00:00Z
review text: Summary: Two novel nonlinear circuits that exhibit an all-positive pinched hysteresis loop are proposed. These circuits employ two NMOS transistors, one of which operates in its triode region, in addition to two first-order filter sections. We show the equivalency to a charge-controlled resistance (memristance) in a decremental state via detailed analysis. Simulation and experimental results verify the proposed theory.
Mathematics Subject Classification ID: 94C05
zbMATH DE Number: 6798532
zbMATH Keywords: nonlinear circuits
zbMATH Keywords: all-positive pinched hysteresis loop
zbMATH Keywords: NMOS transistors
zbMATH Keywords: charge-controlled resistance (memristance)
MaRDI profile type: Publication
full work available at URL: https://doi.org/10.1155/2017/7863095
OpenAlex ID: W2743937810
description: scientific article; zbMATH DE number 6798532